module syn_fifo_tb();
    reg resetn;
    reg clk;

    reg wvalid;
    reg [31:0] wdata;
    reg [1:0] rready;
    reg pready;

    wire wready;
    wire [1:0] rvalid;
    wire pvalid;
    wire [63:0] rdata;
    wire [31:0] pdata;

    initial begin
        clk = 1'b0;
        resetn = 1'b0;
        #2000;
        resetn = 1'b1;
    end
    always #5 clk=~clk;

    initial begin
        wvalid = 1'b0;
        rready = 2'd0;
        pready = 1'b0;
        #2000;
        wvalid = 1'b1;
        rready = 1'b1;
        pready = 1'b1;
    end
    always #10 wdata = $random();

    syn_fifo #(
        .MULTI_RWAY(0),
        .DEPTH(4),
        .WIDTH(32)
    ) syn_fifo (
        .clk(clk),
        .rst(~resetn),

        // write port
        .wvalid(wvalid),
        .wready(wready),
        .wdata (wdata ),

        // read port(multi way)
        .rvalid(rvalid),
        .rready(rready),
        .rdata (rdata ),

        // pop port
        .pvalid(pvalid),
        .pready(pready),
        .pdata (pdata )
    );
endmodule